Microelectronic packages are generally required to have a low z-height and low warpage to allow for solder mount onto a motherboard and reliable operation thereafter. A package-on-package (PoP) architecture that includes a memory component mounted on top of a die of the microelectronic package increases the height of the microelectronic package, thereby making a low z-height requirement more challenging.
A first conventional technique for reducing warpage involves adding core material to an organic substrate of the microelectronic package in order to reduce the coefficient of thermal expansion (CTE) of the organic substrate. This technique, however, tends to significantly increase the z-height of the resulting microelectronics package.
Other conventional techniques for reducing warpage involve adding either a metal stiffener or an organic substrate interposer on top of the die of the microelectronic package. These techniques not only significantly increase the z-height of the microelectronics package but also introduce significant processing challenges for attaching these additional layers on top of the die and managing the reliability of the interfaces. Further, these techniques can result in the consumption of valuable real estate on the package surface which can lead to an even larger package that can exacerbate warpage issues and also increase costs.
Coreless substrates are often used in microelectronic packages to reduce z-height. However, use of coreless substrates can lead to increased warpage of the microelectronics package. Conventional techniques for reducing warpage of microelectronics packages that include coreless substrates generally increase the z-height or introduce additional complex processing steps.
Accordingly, new techniques for reducing warpage of microelectronics packages that may include coreless substrates while maintaining a low z-height may be needed.